Prior art data transfer systems, such as the system 100 shown in FIG. 1, often contain a precharging transistor 102 coupled to a data bus 104 for precharging the bus to a logic high level, e.g., 5 volts. This approach normally assumes that it is faster to pull the bus voltage down to a logic low level, e.g., 0 volts, from the logic high level, than the reverse. Pull-down transistors 106, 110 and 114 connected to bus logic blocks 108, 112 and 116, respectively, are operated to pull the bus voltage down to the logic low level by creating conduction paths to ground when activated.
Data bus 104 is maintained at a logic high voltage, which voltage is nearly instantaneously available at an input of an inverter 118. The data bus is pulled down when a logic low voltage is to be provided to the inverter. Precharging can thus increase the operating speed of data transfer systems.
However, repeated precharging cycles without the intervention of a pull-down operation can raise the precharge voltage to such a high level that the overall advantage of precharging is lost since the time for going from the logic high voltage to the logic low voltage is directly proportional to the precharge voltage. Even where there is not repeated precharging, the bus transition time for changing from the logic high voltage level to the logic low voltage level, and vice versa, may still be undesirably large for some high speed applications.
A bus driver circuit providing increased data transfer speed is presented in U.S. Pat. No. 5,179,299, titled "CMOS Low Output Voltage Bus Driver", which issued to Donald G. Tipon on Jan. 12, 1993, and is assigned to NCR Corporation of Dayton, Ohio. U.S. Pat. No. 5,179,299, which is expressly incorporated by reference, discloses for use in a high speed digital computer data transfer system, a complementary metal oxide semiconductor (CMOS) implemented data bus driver which reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Positive and negative overshoot of the reduced bus logic levels are prevented by "clamping diode" transistors. The data bus driver assumes a tri-state mode when not transmitting data, during which the clamping diode transistors also eliminate positive and negative bus voltage overshoot.
The circuit described in the incorporated reference provides superior operation over previous bus driver circuits. However, applicant has identified several features of the identified circuit which present an opportunity for enhanced performance. First, the conduction thresholds of the output transistors in CMOS bus driver circuits, such as the circuit shown in the incorporated reference, are influenced by variations in process, temperature and voltage, thus changing the clamping voltages, which may result in undesirable DC currents between bus drivers and clamping output drivers. Second, as a result of biasing the gate of the overshoot clamping transistor with the output node voltage, the driver load capacitance may be higher than desirable. And third, bus pull-up times may be slower than desirable since the CMOS N-channel output pull-up transistor has insufficient gate voltage, as CMOS processes tend to migrate to lower power supply voltages.